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Integrated Circuit Systems, Inc.
ICS9148-46
Pentium/ProTM System Clock Chip
General Description
The ICS9148-46 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-03, and -12. There are two PLLs, with the first PLL capable of spread spectrum operation. Spread spectrum typically reduces system EMI by 8-10dB. The second PLL provides support for USB (48MHz) and 24MHz requirements. CPU frequencies up to 100MHz are supported. The I2C interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. Clock outputs include two CPU (2.5V or 3.3V), five PCI (3.3V), two REF (3.3V), one 48MHz, and one selectable 48_24MHz.
Features
Generates system clocks for CPU, PCI, 14.314 MHz, 48 and 24MHz. Supports single or dual processor systems Skew from CPU (earlier) to PCI clock 1 to 4ns Separate 2.5V and 3.3V supply pins 2.5V outputs: CPU 3.3V outputs: PCI, REF No power supply sequence requirements 28 pin SSOP Spread Sectrum operation optional for PLL1 CPU frequencies to 100MHz are supported.
Block Diagram
Pin Configuration
28 pin SSOP
Power Groups
VDD = Supply for PLL core VDD1 = REF(0:1), X1, X2 VDD2 = PCICLK_F, PCICLK (0:3) VDD3 = 48MHz, 24/48MHz VDDL = CPUCLK (0:1)
Ground Groups
GND = Ground Source Core, CPUCLK (0:1) GND1 = REF(0:1), X1, X2 GND2 = PCICLK_F, PCICLK (0:5) GND3=48MHz, 24/48MHz
Pentium is a trademark on Intel Corporation. 9148-46 Rev E 4/20/99
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9148-46
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6, 7, 9, 10 8 11 12 13 14 15 16 17 18 19 20 21 22 23, 24 25 26 27 28 PIN NAME GND1 X1 X2 GND2 PCICLK_F PCICLK (0:3) VDD2 VDD3 48MHz 24_48MHz GND3 SEL100/66.6# SCLK SDATA PD# CPU_STOP# PCI_STOP# GN D VDD CPUCLK (1:0) VDDL REF1 VDD1 REF0 SEL 48# TYPE PWR IN OUT PWR OUT OUT PWR PWR OUT OUT PWR IN IN IN IN IN IN PWR PWR OUT PWR OUT PWR OUT IN DESCRIPTION Ground for REF (0:1), X1, X2. XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output. Not affected by PCI_STOP# PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Poer for 48MHz Fixed CLK output @ 48MHz Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz if pin 27=0 at power up. Ground for 48MHz Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Clock input for I2C input Data input for I2C input Asynchronous input when driven active (LOW) disables internal clocks, stops VCO early. All outputs are placed in a LOW state at the end of the curent cycle. Asynchronous input when driven active (LOW) stops CPUCLK(0:1) in a LOW state. Asynchronous input when driven active (LOW) stops PCICLK(0:3) in a LOW state. PCICLK_F is not affected. Ground for CPUCLK (0:1) and the core Power for PLL core CPU and Host clock outputs nominally 2.5V Power for CPU outputs, nominally 2.5V 14.318MHz Reference clock output Power for REF outputs. 14.318MHz clock output Latched input at power up. When low, pin 13 is 48MHz.
2
ICS9148-46
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit

How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
ACK
Byte 1
Byte 1
ACK
ACK
Byte 2
Byte 2
ACK
ACK
Byte 3
Byte 3
ACK
ACK
Byte 4
Byte 4
ACK
ACK
Byte 5
Byte 5
ACK
ACK
Byte 6
Byte 6
ACK
ACK Stop Bit
Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
3
ICS9148-46
Serial Bitmap
Byte 3: Functionality & Frequency Select & Spread Slect Register
Bit 7 Description 0: Center Spread 0.255% 1: Down Spread 0 to -0.6% Bit CPU PCI 654 34.25 68.5 000 37.5 75.0 001 41.6 83.3 010 33.3 66.6 011 34.3 103 100 37.3 112 101 44.43 133.3 110 33.33 100 111 0 - Frequency is selected by hardware select SEL100/66.6# 1 - Frequency is selected by 6:4 above (Reserved) 00 - Normal operation 01 - Test mode 10 - Spread sprectrum ON 11 - Tristate all outputs PW D 0
Byte 5:
Bit 7 6 5
Pin# 5 10 9 7 6 -
Pin Name PCICLK_F PCICLK3 PCICLK2 PCICLK1 PCICLK0 -
PWD 1 1 1 0 1 1 0 0
6:4
0
4 3 2
3 2 10
0
1 0
Description Bit Value = 0 Bit Value = 1 Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) (Reserved) (Reserved) Disabled Enabled (low) Disabled Enabled (low) (Reserved) (Reserved) (Reserved) (Reserved)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
00
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 4:
Bit 7 6 5 4 3 2 1 0 Pin# 23 24 Pin Name CPUCLK1 CPUCLK0 PWD 1 0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) (Reserved) (Reserved) (Disabled) Enabled (low)
Byte 6:
Bit 7 6 5 4 3 2 1 0 Pin# Pin Name PWD 26 28 REF1 REF0 0 0 0 0 0 1 0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Disabled) Enabled (low) (Reserved) (Reserved) (Disabled) Enabled (low)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Notes: 1 = Enabled; 0 = Disabled, outputs held low
4
ICS9148-46
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to VDD +0.5 V 0C to +70C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time1 Clk Stabilization 1 Skew1
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 IDD3.3PD Fi CIN CINX Ttrans Ts TSTAB TAGP-PCI1
CONDITIONS
MIN 2 VSS-0.3
TYP
MAX VDD+0.3 0.8 5
UNITS V V A A A mA mA A MHz pF pF ms ms ms ns
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V;
-5 -200
0.1 2.0 -100 60 66 3 14.318
170 170 650
27
36 5
5 45 3 3 4
1
3.5
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current Skew
1 1
SYMBOL IDD2.5OP66 IDD2.5OP100 IDD2.5PD tCPU-AGP tCPU-PCI2
CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; With input address to Vdd or GND VT = 1.5 V; VTL = 1.25 V
MIN
TYP 16 23 10
MAX 72 100 100 1 4
UNITS mA mA A ns ns
0 1
0.5 2.6
Guaranteed by design, not 100% tested in production.
5
ICS9148-46
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1 dt2B1 tsk2B1 tjcyc-cyc2B1 tj1s2B1 tjabs2B1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19
45
-250
TYP 2.3 0.2 -41 37 1.25 1 48 30 150 40 140
MAX UNITS V 0.4 V -19 mA mA 1.6 ns 1.6 ns 55 % 175 ps 250 ps 150 ps +250 ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tj1s1 tjabs1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
16
TYP 3.1 0.1 -62 57 1.5 1.1
MAX UNITS V 0.4 V -22 mA mA 2 2 55 500 150 500 ns ns % ps ps ps
Duty Cycle
45
50 140 17
Jitter, One Sigma Jitter, Absolute
1
1
-500
70
Guaranteed by design, not 100% tested in production.
6
ICS9148-46
Electrical Characteristics - REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.6
29
TYP 3.1 0.17 -44 42 1.4 1.1
MAX UNITS V 0.4 V -22 mA mA 2 2 57 3 5 ns ns % % %
Duty Cycle
47
54 1 3
Jitter, One Sigma Jitter, Absolute
1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48, 24 MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.6
16
TYP 3 0.14 -44 42 1.2 1.2
MAX UNITS V 0.4 V -22 mA mA 4 4 55 3 5 ns ns % % %
Duty Cycle
45
52 1 3
Jitter, One Sigma Jitter, Absolute
1
1
Guaranteed by design, not 100% tested in production.
7
ICS9148-46
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended.
Capacitor Values: C1, C2 : Crystal load values determined by user All unmarked capacitors are 0.01F ceramic
8
ICS9148-46
SYMBOL MIN. A A1 A2 b c D E e H L N 0.068 0.002 0.066 0.010 0.004 0.205 0.301 0.025 0
COMMON DIMENSIONS NOM. 0.073 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4 MAX. 0.078 0.008 0.070 0.015 0.008 0.212 0.311 0.037 8
VARIATIONS N 14 16 20 24 28 30 MIN. 0.239 0.239 0.278 0.318 0.397 0.397
D NOM. 0.244 0.244 0.284 0.323 0.402 0.402 MAX. 0.249 0.249 0.289 0.328 0.407 0.407
28 Pin SSOP Package Ordering Information
ICS9148yF-46
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
9
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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